| Name | Version | Summary | date |
| cocotb-yaml-runner |
0.1.1 |
YAML-based test runner for cocotb with Verilator |
2025-10-25 16:09:43 |
| klever |
0.1.0a1 |
Kit for Less-Effort Verification |
2025-10-19 09:02:40 |
| pyrilog |
0.2.4 |
A Python-based SystemVerilog code generator using context managers |
2025-09-09 18:02:31 |
| jtag-axi |
0.1.5 |
JTAG to AXI bridge python I/F |
2025-08-20 09:29:31 |
| mooreio-client |
2.1.9 |
CLI tool to automate EDA tasks for ASICs, FPGAs, and UVM IP. |
2025-08-19 02:13:13 |
| torii-boards |
0.8.1 |
Supplementary FPGA Board Files for Torii |
2025-08-13 21:25:22 |
| pytcl-eda |
0.3.0 |
PyTCL allows control EDA tools directly from Python that use TCL |
2025-08-11 07:27:29 |
| hdltree |
0.5.2 |
Pure Python HDL parser, plus symbol generator and sphinx domain |
2025-07-13 23:19:51 |
| cache-performance-model |
0.1.3 |
Cache performance model |
2025-02-24 01:39:18 |
| slvcodec |
0.4.20 |
Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python. |
2025-01-30 03:04:09 |
| cocotbext-ahb |
0.4.9 |
CocotbExt AHB Bus VIP |
2025-01-25 18:58:04 |
| edalize |
0.6.0 |
Library for interfacing EDA tools such as simulators, linters or synthesis tools, using a common interface |
2024-11-13 20:05:24 |
| cocotbext-waves |
0.1.9 |
CocotbExt Wavedrom diagram generator |
2024-11-01 20:03:31 |
| fusesoc |
2.4 |
Award-winnning package manager and build abstraction tool for HDL code |
2024-10-02 17:49:41 |
| smolarith |
0.2.0 |
Soft-core arithmetic components written in Amaranth HDL |
2024-06-26 05:09:51 |
| mio-cli |
1.3.8 |
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA/ASIC projects. |
2024-05-17 12:13:59 |
| magia-flow |
0.2.0 |
Design flow integration and automation with Magia |
2024-05-11 21:01:26 |
| openflex |
0.1.4 |
Framework for Logic Synthesis and EXploration |
2024-03-24 05:02:05 |